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TMS320 C6000 DSP结构原理与硬件设计

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《TMS320 C6000 DSP结构原理与硬件设计》可作为电子信息、通信工程、汁算机应用及自动控制等专业高年级本科生或研究生的教学参考书,也可供从事DSP应用系统设计的科技术人员使用。
Content Description

介绍TI公司的TMS320 C6000系列DSP的结构原理和硬件设计方法,主要以定点C62X和浮点C67X为描述对象, 全面剖析高度并行的CPU内核、分层次的存储器结构和丰富的集成外围模块,详细分析CPU、存储器,EDMA、EMIF、HPI、McBSP、McASP、I2C总线,GPIO、定时器、扩展总线、PCI总线、锁相环和节能逻辑等部分的结构原理与使用方法,并给出基于C6713 DSP的实际应用系统的硬件设计实例。
本书可作为电子信息、通信工程、计算机应用及自动控制等专业高年级本科生或研究生的教学参考书,也可供从事DSP应用系统设计的科技术人员使用。
Catalogue

第1章 TMS320 C6000系列DSP简介
1.1 概述
1.2 C6000 DSP的定点和浮点系列及代码兼容性
1.3 TMS320 C6000 DSP技术特征
1.3.1 高度并行的CPU结构
1.3.2 灵活的存储器配置
1.3.3 丰富的外设模块
1.4 本书的结构安排与导读
第2章 中央处理单元CPU工作原理分析
2.1 CPU的组成单元
2.2 CPU的程序执行机构 数据通道
2.2.1 通用寄存器组A和B
2.2.2 功能单元与指令映射
2.2.3 寄存器组交叉路径
2.2.4 数据存储器的读取和存储路径
2.2.5 数据地址路径与寻址方式
2.3 CPU的取指、译码与分配机制一流水线操作
2.3.1 取指阶段
2.3.2 译码阶段
2.3.3 执行阶段
2.4 控制寄存器
2.5 中断控制与中断选择
2.5.1 中断类型与优先级
2.5.2 有关中断的控制寄存器
2.5.3 中断服务表
2.5.4 中断选择
第3章 C6000 DSP内部存储器结构分析
3.1 C6000 DSP的存储器映射
3.2 C620X/C670X DSP片内存储器结构
3.2.1 片内程序存储器的管理与工作模式
3.2.2 C620X/C670X DSP的片内数据存储器
3.3 C621X/C671X DSP片内分层的存储器结构
3.3.1 第一级数据缓存LlD
3.3.2 第一级程序缓存L1P
3.3.3 第二级存储器L2
3.4 存储器的控制寄存器
3.5 高速缓存的管理
第4章 增强的直接存储器访问EDMA结构与原理
4.1 EDMA概述
4.1.1 直接存储器访问
4.1.2 增强型直接存储器访问
4.2 EDMA基本结构
4.2.1 EDMA的组成
4.2.2 参数RAM体说明
4.3 EDMA控制寄存器
4.3.1 EDMA事件选择寄存器ESE1
4.3.2 EDMA优先级队列状态寄存器PQSR
4.3.3 EDMA通道中断挂起寄存器CIPR
4.3.4 EDMA通道中断使能寄存器CIER
4.3.5 EDMA通道链接使能寄存器CCER
4.3.6 EDMA事件寄存器ER
4.3.7 EDMA事件使能寄存器EER
4.3.8 EDMA事件清除寄存器ECR
4.3.9 EDMA事件设置寄存器ESR
4.4 EDMA的传输过程
4.4.1 EDMA的初始化与启动
4.4.2 EDMA传输的同步控制
4.4.3 EDMA传输的类型
4.4.4 单元大小和汁数更新
4.4.5 源地址/目的地址更新
4.4.6 链接和终止一个EDMA传输
4.4.7 EDMA的性能分析
4.5 快速直接存储器访问工作原理
4.5.1 初始化一个QDMA传输
4.5.2 QDMA寄存器
4.5.3 QDMA性能分析和优先级
4.6 EDMA应用实例
4.6.1 单元同步的一维到一维数据传输
4.6.2 阵列同步的二维到二维数据传输
4.6.3 块同步的一维到二维数据传输
第5章 外部存储器接口EMIF结构原理与使用
5.1 EMIF概述
5.2 EMIF接口信号与说明
5.3 EMIF的控制寄存器
5.3.1 EMIF全局控制寄存器GBICTL
5.3.2 EMIFCE空问控制寄存器CECTI.0~3
5.3.3 EMIF SDRAM控制寄存器SDCTI
5.3.4 EMIF SDRAM时序控制寄存器SDTIM
5.3.5 EMIF SDRAM扩展寄存器SDEXT
5.4 EMIF与存储器的接口及时序说明
5.4.1 存储器宽度
5.4.2 EMIF存储请求优先级
5.4.3 EMIF的SDRAM接口及时序说明
5.4.4 EMIF的SBSRAM接口及时序说明
5.4.5 EMIF的ASRAM接口
5.5 EMIF使用实例
5.5.1 EMIF与异步FIFO存储器的接口实例
5.5.2 EMIF与FLASH存储器接口实例
第6章 主机接口HPI的结构原理与应用
第7章 多通道缓冲串行口McBSP结构原理与应用
第8章 多通道音频串行口McASP结构原理与应用
第9章 定时器结构与工作原理
第10章 12C模块的原理与使用
第11章 通用目的输入输出GPIO的功能分析
第12章 外围设备互连PCI接口原理
第13章 扩展总线XBUS的原理和应用
第14章 锁相环控制器和节能模式的工作原理
第15章 C6000 DSP应用系统的硬件设计
附 录 TMS320 C6713 DSP分组信号描述
参考文献
Book Abstract

第1章TMS320 C6000系列DSP简介
在概括DSP特点和TMS320 DSP产品系列的基础上首先说明TMS320 C6000 DSP的定点和浮点系列及其代码兼容性;然后从高度并行的CPU结构、灵活的存储器配置和丰富的外围模块等角度,详细阐述TMS320 C6000系列DPS的技术特征;最后介绍本书的结构安排,指导读者阅读。
1.1概述
数字信号处理器DSP(Digital Signal Processor)是一种具有特殊结构的微处理器,它专门 为实现数字信号处理的各种算法而设计?因而在硬件结构上具有特殊性,如内部存储器采用程序总线和数据总线分开的哈佛结构。由于程序存储器和数据存储器在物理上是两个独立的存储区域,可使取数据和取指令同时进行,大大提高处理器的处理能力;具有专门的硬件乘法器,容易完成数字信号处理中诸如卷积、滤波、FFT等算法中的乘法和累加基本运算;广泛采用流水线操作,把一条指令分成取指、译码和执行等阶段.实现多条指令并行运行,缩短指令执行时间。DSP因其独特优点,已被广泛应用在信号处理、通信、雷达、自动控制及生物医学等领域。随着性能价格比的日益提高,DSP显示出巨大的应用潜力。
美国德州仪器公司(Texas Instruments,简称TI)是世界上生产DSP芯片的主要公司之一。TI公司自1982年推出第一代TMS32010、TMS32011、TMS320C10/C14/C15/C16/C17等DSP芯片之后,相继又推出第二代DSP芯片TMS32020和TMS320 C25/c26/C28,第三代DSP芯片TMS320 C30/C31/C32,第四代DSP芯片TMS320 C40/C44,第五代DSP芯片TMS320 C5x/C54X,第二代DSP芯片的改进型TMS320 C2XX,集多片DSP芯片于一体的高性能TMS320 C8X以及目前速度最快的第六代DSP芯片TMS320 c62x/C64X/c67x等。TI公司将常用的DSP芯片归纳为三大系列:即TMS320 2000系列(包括TMS320 c2X/TMS320 C2XX/TMS320 C24x/TMS320 C28X等)、TMS320 C5000系列(包括TMS320C54X/C55X)和TMS320 C6000系列(包括TMS320 C62X/C64X/C67X)。TI公司的DSP芯片系列如图1—1所示。
Introduction

TMS320 C6000系列DSP是TI公司的TMS320 DSP家族的重要系列。该系列DSP芯片的CPU采用多功能单元并行和支持多级流水线的VLIW结构,拥有大寻址范围的片内和片外分层的存储器体系,集成了丰富的组件和外围功能模块。其结构先进、性价比高,广泛应用于通信、图像/视频处理、语音处理、雷达、声纳、医疗设备及自动控制等方面。
本书以C6000系列DSP中的定点C62X DSP和浮点C67X DSP为描述对象,全面介绍其内部硬件结构、工作原理、寄存器定义和设置,并给出使用方法和设计实例;详细分析中央处理单元CPU、片内分层的存储器、增强的直接存储器存取EDMA、外部存储器接口EMIF、主机接口HP1、多通道缓冲串行口McBSP、多通道音频串行口McASP、I2C总线模块、通用输入/输出GPIO接口、定时器、扩展总线XBUS、PCI总线、锁相环PLL和节能逻辑(Power—Done)等部分的结构原理与硬件设计方法,并给出基于C6713 DSP的HFC网络反向通道噪声频谱实时检测系统的设计实例。
对每部分的描述都采用由外及里、从整体到局部再到整体的路线,先概括其组成结构和对外引脚,再详述相关寄存器的定义与设置,然后结合硬件结构和寄存器设置说明模块的原理与工作过程,最后给出模块的使用方法和应用实例。

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